1. Field of the Invention
The invention relates to a digital to analog converter (DAC), and more particularly, to a DAC with reduced errors among a plurality of digital to analog converting units.
2. Description of the Related Art
A digital to analog converter (DAC) is typically composed of several DAC elements, which receive digital input data and generate element signals according to the digital input data. The element signal can be voltage type or current type. Then, a signal integrator (or a summing node) adds the element signals outputted from the DAC elements and generates an analog output signal.
FIG. 1 illustrates a schematic diagram of a conventional DAC. As shown in FIG. 1, the DAC 10 includes a plurality of DAC elements, i.e., current sources E1˜En, a plurality of switches SA1˜SAn, and a summing node 11. The ON/OFF state of each of the switches SA1 to SAn is controlled by each bit of the digital input data. The ON/OFF state of each of the switches SA1 to SAn determines the connection relationship between each of the DAC elements E1 to En and the summing node 11. The summing node 11 generates an analog output signal according to the connected element signals. Therefore, the digital input data controls the ON/OFF state of each of the switches SA1 to SAn so as to generate the corresponding analog output signal. The DAC 10 is widely used in several fields, such as the fields of communications, voice-frequency, radio frequency, and the like. In some applications, two or more DACs with a small error therebetween are required.
FIG. 2 illustrates a conventional DAC system with two DACs. The conventional DAC system 20 has two DACs 21 and 22 with the same structure and components to generate two analog output signals. Owing to the variations such as those happened in manufacturing process, it tends to be errors between the two analog output signals even with the two digital input data being the same. The error is unacceptable if it exceeds an allowable range. For example, in the application of the radio intranet (IEEE 802.11a), the error requirement between the DACs of the I-channel transmitter and the Q-channel transmitter has to be smaller than 0.1%.